(1) Field of the Invention
This invention relates to an integrated circuit semiconductor device, and more particularly to a method for fabricating an array of memory cells for dynamic random access memory (DRAM) devices with semicrown-shaped capacitors having increased capacitance.
(2) Description of the Prior Art
The integrated circuit density on chips formed on semiconductor substrates has dramatically increased in recent years. The increase in density is the result of scaling down the individual semiconductor devices built in and on the substrate.
One circuit type experiencing this demand for increased circuit density and the need for an essentially planar surface is the dynamic random access memory (DRAM) chip (or devices) made on a semiconductor substrate. The DRAM chip areas on the substrate consist of an array of closely spaced memory cells with address and read/write circuits along the periphery of the chip. Currently in production there are 64 million memory cells on a DRAM chip with minimum features sizes less than a half micrometer. The individual memory cells are formed from a single access transistor, typically a field effect transistor (FET), and a storage capacitor with a node contact to one of the two source/drain areas of the FET. The capacitor is used for storing information in binary form (0's and 1's) as electrical charge, and the second source/drain area is connected to a bit line that is used to read and write information via peripheral circuits on the DRAM chip. Word lines that also form the FET gate electrodes are used to randomly access (address) the individual memory cells.
Both trench capacitors formed in the substrate and stacked capacitors formed on the substrate surface over the FET are currently being pursued for DRAM applications. However, the stacked capacitor has received considerable attention in recent years because of the various ways its shape can be changed in the vertical direction to increase capacitance without increasing the area it occupies on the cell area. However, as the cell density increases and the cell size shrink to accommodate more cells, it is necessary to increase the vertical dimension of the stacked capacitor. This is to provide sufficient capacitance to maintain the necessary charge for acceptable sign-to-noise levels and to provide a reasonable refresh cycle times.
Unfortunately, as the stacked capacitors are increased in height the topography across the chip becomes rougher, and the problem associated with reliably exposing the photoresist and etching high-aspect-ratio patterns in the material layers are made more difficult. Although the spaces between the closely spaced capacitors in the memory cell area can be easily filled with an insulator to provide a relatively planar surface, the topography at the perimeter of the array cell near the periphery of the chip can be considerably greater than 1.0 micrometer in height. Another problem is when freestanding bottom electrodes are formed, subsequent processing, such as cleaning and the like, can result in mechanical damage.
Numerous methods for making the stacked capacitors are described in the literature. One approach to forming stacked capacitors is described by Kim et al., U.S. Pat. No. 5,444,005. The method shows a sequence of process steps for forming a multiwalled cylindrical freestanding bottom electrode using multiple sidewall spacers. Another approach for making stacked capacitors is described by Liaw et al. in U.S. Pat. No. 5,543,345, which also uses sidewall spacers for forming freestanding sidewalls for the bottom electrode of a crown capacitor. Still another approach is described by Tseng in U.S. Pat. No. 5,604,146 for an E-shaped crown capacitor using sidewall spacers and a second photoresist mask to etch freestanding bottom electrodes. Dennison et al., U.S. Pat. No. 5,270,241, show a method for forming container stacked capacitors in the node contacts etched in an insulating layer. The insulating layer is then partially etched back, without an etch-stop layer, to leave portions of the insulating layer as a protective layer over the underlying devices.
There is still a need in the semiconductor industry to develop a method for making stacked capacitors that are less susceptible to mechanical damage. There is also a need to provide a process that forms a more planar surface over the substrate for improved high-resolution lithography and residue-free anisotropic etching.